clk_duty=P50, clk_count_mode=oscl
TWI_DRV Bus Control Register
sda_moe | SDA manual output enable |
scl_moe | SCL manual output enable |
sda_mov | SDA manual output value |
scl_mov | SCL manual output value |
sda_sta | SDA current status |
scl_sta | SCL current status |
clk_m | |
clk_n | |
clk_duty | Setting duty cycle of clock as master 0 (P50): 50% 1 (P40): 40% |
clk_count_mode | 0 (oscl): scl clock high period count on oscl 1 (iscl): scl clock high period count on iscl |